Embedded Systems November 2000 Vol13_12

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I i * = The network processor industry is at an early stage. Nevertheless, for developers of networking devices, network processors might be the fastest platform for the next-generation product. co-processors, including tables, queues, buffers, protocols, switch fab- rics, kernel services, and diagnostics. The C-Ware reference library includes C-5 implementations of a gigabit ethernet switch, packet over SONET (POS) switch, and ATM switch. Intel IXP1200 Intel has become a leader in market- ing network processors as part of their Internet Exchange Architecture. Currently, most network processor companies are extremely secretive about their products. Intel is the exception. Of the four network processors described in this article, Intel's IXP1200 is the only one for which you can directly download a datasheet from the Web. The IXP1200, shown in Figure 5, consists of a StrongARM processor, six RISC micro-engines, and inter- faces to SRAM/ SDRAM memory, PCI bus, and Intel's proprietary IX Bus. The IXP1200 has been designed to do fast path and slow path processing in one chip. The StrongARM portion of the proces- sor can be programmed for the slow path with conventional C/ C++ tools. The six micro-engines are designed for fast path processing. Each micro-engine has four hard- ware contexts and can context switch in a single instruction. The micro-engines are limited to 1MB of program space, which is actually quite a bit, since they are pro- grammed in microcode. Intel provides assembly tools for the microcode as well as a simulator for debugging the non-StrongARM parts of the IXP1200. Intel ships the IXP1200 development environment with example code for Layer 2 and Layer 3 bridging and routing. Lucent Lucent's network processor design is very different from the other three network processors described in this article. It is a three-chip solution for the fast path. System designers need to add a general-purpose micro- processor for slow path processing. Lucent's network processor has three parts: the functional pattern processor (FPP), the routing switch processor (RSP) and the Agere sys- tem interface (ASI). Both the FPP and RSP are programmed with 4GLs (fourth-generation languages). See Figure 6. The idea behind the FPP is that there is a large class of network pro- cessing functions that require some sort of pattern matching. This includes parsing packets and searching through routing tables. The RSP handles all actions for a particular packet, includ- ing packet modifications like routing, and traffic management functions like queueing. The ASI is for sending and receiving slow path packets from a gen- eral purpose CPU. Development kits are available that implement the Lucent network processor using five Xilinx Virtex FPGAs. Clocked at 33MHz, they sup- port full duplex OC-12 interfaces. The tools are not the standard C/ C++ development environment that is common with other network proces- sors. The development kit contains: • Functional programming language compiler-for programming the FPP • Agere Scripting Language (ASL) Compiler-for programming RSP and ASI • Java-based simulation environment • Command-line simulators for the FPP and RSP • Traffic generator 60 NOVEMBER 2000 Embedded Systems Programming The Application Code Library includes IP switching and routing over ATM AAL5, over Ethernet, and over Frame Relay. Sitera Sitera's network processor family, tl1e Prism IQ2000 (shown in Figure 7) , consists of four RISC cores, co-proces- sors for lookup, order management, multi-cast support, DMA manage- ment, context management, and interfaces to both SRAM/ RDRAM and a general-purpose CPU. Sitera expects the Prism to handle fast path process- ing and for a CPU to be designed in for slow path processing. The Prism's RISC cores have a modified version of the MIPS instruction set with four hardware contexts. Packet scheduling is han- dled in hardware, with the order management co-processor responsi- ble for resolving packet interdepen- dencies. Sitera offers three varia- tions of the Prism IQ2000, each with the same core but different network interfaces. Sitera's Developer's Workbench is based on the GNU C/ C++ compiler, but also includes a simulator and traf- fic generator. Their reference applica- tion code supports Layer 2 and Layer 3 bridging and routing. Conclusions The network processor industry is at an early stage. Most network proces- sors have only recently started ship- ping production quantities, and only a few shipping products use network processors. Nevertheless, for devel- opers of networking devices, net- work processors might be the fastest platform for the next-generation product. esp Mark Kohler writes networking software in southern California. His interests include computer networking and software engi- neering. He can be reached at kohler@netri-

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