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Embedded Systems November 2000 Vol13_12

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How do you make effective use of multiple RISC cores and hardware acceleration units? Every network processor vendor insists that their design is the easiest to program, so it is good to think critically about this question. TABLE 1 Maximum processing time WAN link T-1 T-3 OC-3 OC-12 OC-48 OC-192 1.5 45 155 622 2,500 9,500 "'- -.~ ··.·-, _ · _ :,>. Data rate (Mbps) • High-speed memory interface(s) • High-speed 1/0 interfaces • In terface to general purpose CPU . • • · • - . 1;.'·.: · gramming models, not to mention sys- but includes traits common to most. tern architecture and what flavors of These traits are: hardware acceleration to include. Figure 2 is a block diagram of a gene ric network processor. It does not represent a specific network processor, FIGURE 4 • Multiple RISC cores • Dedicated hardware for common networking operations Programming a network processor Since network processors are very dif- ferent from general purpose proces- sors, the most important question for programmers is, how do you program it? How do you make effective use of multiple RISC cores and hardware accele ration units? Every network processor vendor insists that th eir design is the easiest to program, so it is good to th ink critically about this question. In many ways, network processor archi tectures look like the parallel processing architectures of a decade ago. Programmers have tried to har- ness the power of parallel proce sing architectures for a long time, but with I ' DCP _.- I __ I C-5 ,' I ' ; ' I ' ,' I .,..._-------- ---.- Processor Boundary Channel Processors SO NOVEMBER 2000 Embedded Systems Programming

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