Embedded Systems November 2000 Vol13_12

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New Products transfer. System I/0 is achieved through two 128-channel synchronous TDM and four serial ports, a 32-bit parallel port that includes a 32-bit SRAM conu·oller, and an SPI inter- face. Clusters of DSPs can be built using the on-chip multiprocessing in te rfaces, which enable global shared memory within the cluster. De igners can also connect up to six SHARC DSPs and a host without designing extra circuitry. The 3.3V device is 5.0V tolerant for I/0. It's sampling now. Analog Devices Norwood, MA (781) 329-4700 Low-power microcontroller The ST72C254 is an 8-bit microcon- troller. It's a low power device with 8KB of flash memory. The ST72C254's program memory is built with a single-supply fl ash technology that allows the microcontroller to be reprogrammed up to 100 times, either by inserting the device into a programming board socket or within the application by means of a stan- dard serial port. Individual bytes can be reprogrammed without erasing the main program. This eliminates the need for an EEPROM to store configuration data. The contents of the program memory can be secured against unauthorized copying by acti- vating a readout protection mecha- nism. A variety of noise immunity option are included, all of which are software selectable when the device is programmed. These include a three- level Low Voltage Detection circuit, a watchdog counter with three operat- ing mode , and a selectable oscillator source, including a fail-safe backup oscillator and reset 01·igin flag that allows the source of a reset to be iden- tified to re tart the application safely. The ST7 core is based on an industry standard architecture, with 63 instructions, including multipli ca- tion, and 11 addressing modes. With a 16MHz clock speed, in truction time is as short as 250ns, with in ter- rupts managed in less that 1.5ps, while typically consuming less than 2mA/ MIPS. The ST72C254 includes 256 bytes of data RAM, two 16-bit timers with input capture, output compare and PWM modes, a 1MBps PI port, an I2C in terface operating at up to 400kHz, a six-chan nel ADC with a conversion time less than 31-ls, and 22 l/0 pins, including eight that can drive 20mA loads. Samples are available now. STMicroelectronics Lexington, MA (781) 861-2650 Software development platform The C2000 is a development platform for DSP motion control engineers. It includes both traditional ROM devices and flash memory-based products with a fl exible set of peripherals. Among these is the TMS320LF2407 flash DSP, which integrates 32Kx 16 words of flash , 2.5KB of RAM, an A/ D with 500ns conversion time, an on-board event manager pro- viding pulse-width modulation (PWM) and l/0 features to d1;ve all motor types, and several other control-optimized peripherals like watchdog timer, SPI, SCI, and CAN. Another part of the C2000 platform is the C28x DSP core, which offers up to 400 MIPS of compu- tational bandwidth to handle numerous real-time control algorithms, such as sen- orless speed control, random PWM, and power factor correction. The plat- form is designed for use with the eXpressDSP open software platform, which allows motor drive manufacturers to use a library of DSP motor control oftware modules that conform to a defined standard for interoperability. Texas Instruments Dallas, TX (800) 336-5236 160 NOVEMBER 2000 Embedded Systems Programming Commumcabons chip The QuickSD family is a series of chips for communications applica- tions. They in tegrate multi-channel serial communications links with embedded memory, MAC blocks, and customizable logic. The devices embed up to 10 LVDS transceivers- eight bus LVDS data SERDES chan- nels and two clock bus LVDS links. With each data channel supporting up 1Gbps speeds, QuickSD devices deliver up to 8Gbps total bandwidth. They also include customizable logic, memory, and MAC block. Quick Logic Sunnyvale, CA (408) 990-4000 www. qu icklogic. com IP Core The Internet Tuner Ethernet intel- lectual property core is an Internet system-on-a-chip with Ethernet capa- bilities. It features a soft core, pre- configured drop-in design that can be used as a stand-alone chip or can be embedded in other appli cation- specific ilicon. It off loads MIPS from host proce sors. Along with an Ethernet PHY, Internet Tuner Ethernet provides non-PC devices with the protocols necessary to con- nect to-and send and receive data over-the Internet in a networked environment. The core uses stream- ing byte architecwre for TCP/ IP network proces ing and adds ARP, host IP routing, and an 802.3 Ethernet MAC. In addition to the hardware protocol stack, the Internet Tuner Ethernet contai ns a protocol engin e, system peripherals, and a set of accelerators that allow for integrated network applicatio n systems. iReady Santa Clara, CA (408) 330-9450

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