Embedded Systems September 2000 Vol13_10

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N z LlmNG 7 Context switch on the eZ80 · . eZBO_Context_Swi tch: Save the current task's context PUSH main register set PUSH secondary register set Save SP into the TCB of the task to suspend; Restore the new task's context Load SP from the TCB of the task to resume; POP secondary register set POP main register set RET adjacent memory locations. Furthermore, the compiler takes care of mo t of the memory banking work for you. However, from a program- mer' standpoint, l sure like the linear addressing scheme of the eZ80. I like the Rabbit's multiple inter- rupt priority scheme and especially the fac t that you can save and restore the state of the interru pt level on the stack. This means that if you have interrupts disabled before making a call to the kernel, interrupts would be disabled upon return from the kernel. one of the other processors provide this feature. Table 1 shows the execution time (in clock cycles) for some instructions that a kernel would use as well as the execution time fo r a context switch (assuming r C/ OS-II) for each proces- sor. The 180-class processor is faster than the Z80 by about 5%. The Rabbit is about 25% fas ter than a Z80. The eZ80 is more than twice as fast as the Z80 and assumes ADL mode. However, the execution times for the eZ80 resulted from preliminary data that is subject to change. A context switch is cer- tainly not representative of the true performance of a processor and should thus not be considered, by any means, to be an extensive benchmark. A context switch only measures how fast registers can be saved and re tored to/ from the stack. It remains to be seen whethe r ZiLOG will deliver on its promise of an 80MHz part. If they do, one has to wonde r about th e memory speed required to feed this device. Some of the eZ80 instructio ns a re single cycle. This means that at 80MHz, the eZ80 would read or write from/ to memory in less than 12.5ns (in fact, much less if you conside r propaga- tion delays, setup, and hold times) . It's my understanding that the fastest flash chi ps have a 35ns access time. This would mean that, at 80MHz, you woul d need to add wait-states to stretch memory accesses by at least four clock cycl es. This would defeat th e whole id ea of getting a fas t processor. l f you include op-code fetches, it's easy to see how a 5-byte instruction could take at least 20 clock cycles (not fi ve) . To obtain sin- gle-cycle byte reads and writes on comme rciall y available 35ns fl ash chips, I beli eve th at ZiLOG only needs to come out with 20MHz par ts (at best). Of course, your design could boot from slowe r fl ash but run out of fast, but expensive, static RAM if you need to get every ounce of per- formance out of th e eZ80. The Z80 has always been a decent processor to use with a kernel. It offe rs great addressing modes, plenty of reg- isters and a good set of instructions. We seem to always ask more of the processor · we choo e and hopefu lly, these new generations of Z80 proces- sors will help quench this need. esp Jean Labrosse is a senior technical staff member at Dynalco Controls in Fort Lauderdale, FL. Dynalco is a manufactur- er of electronics equipment that serves the oil and gas industry. He has a master's degree in electrical engineering and has been designing embedded systems f or many yean. Labrosse is the author of two books jJublished by R&D Technical Books: MicroC/ OS-II, The Real-Time Kernel and Embedded Systems Build ing Block , Complete and Ready-to-Use Modules in C. Contact him at ]Labrosse@Dynalco. com. TABLE 1 !:lead-to-head chip comP.arison Disable interrupts Multiply Load A with memory pointed to by HL Load SP with contents of HL Push 16-bit register on stack Pop 16-bit register from stack Increment memory pointed to by IX Call function Jump Return from function Return from interrupt IJCIOS- 11 context switch 66 SEPTEMBER 2000 Embedded Systems Programming Dl MLT Load memory pointed to by IX with contents of register LD (IX+ d), r 8-bit register move LD r,s LD A, (HL) lD SP, HL PUSH dd POP dd INC (IX+ d) CALL nn JP nn RET RETI N/A 4 4 N/A 19 4 7 6 11 10 23 17 10 10 14 426 3 3 17 14 4 6 4 11 9 18 16 9 9 13 400 2 2 12 10 2 5 2 10 7 12 12 7 8 12 330 1 1 5 4 1 2 1 4 4 6 7 6 6 7 163

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