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Embedded Systems September 2000 Vol13_10

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The eZ80 has a more convenient addressing scheme than either the 180-class processors or the Rabbit 2000 and offers a larger linear address space (16MB vs. 1MB). ~STING6 Context switch on the Rabbit 2000 · " Rabbit __ Context __ Switch: Save the current task's context PUSH main register set PUSH secondary register Get XPC and PUSH Get STACKSEG and PUSH Save SP into the TCB of the task to suspend; Restore the new task's context Load SP from the TCB of the task to resume; POP and set STACKSEG POP and set XPC POP secondary register set POP main register RET in Figure 10. The eZ80 is thus able to address up to 16MB of memory linear- ly without resorting to banking schemes. In addition, the address space can contain eitl1e1 - code or data. The eZ80 only has an 8-bit wide data bus. Thus, obtaining a 24-bit add• ·es will require slightly more execution time tl1an the ot!1er Z80 derivatives. I believe that this is a small price to pay to get t!1e convenience that t!1e eZ80 gives you. As you would expect, the 24-bit reg- isters can also be used to contain data. This allows you to perform certain 24- bit arithmetic operation . Another nice feature of the eZ80 is its inclusion of the ZiLOG Debug Interface. This is a two-pin interface t!1at allows debug- ging without requiring an in-circuit emulator. Listing 7 shows the pseudo-code FIGURE 1 ~ "'===--=24 Bits r - ,- Ma!n Register Set A -~ BC ~~ ------------- -------- F ~ ·j Alternate Register Set _A'_ _ _1 F' BC' ~--- - --,X ------'-,y 11-----·-- - - - 24 Bits SP -- -~ ------·- R II ! - ----- ---~ '5I I l ; : I at speeds of up to 80MHz. ZiLOG claim that the eZ80 will execute code four times faster than a tan- dard Z80 ope• ·ating at the same clock speed. The eZ80 offers binary com- patibility modes with the Z80 and the Zl80. ZiLOG added a few new instructions to the architecture but nothing spectacul ar. S me eZ80 derivative processors will be available with a 40-bit multiply- and-accumulate (MAC) engine. Information on the MAC is very pre- liminary. The MAC will act as a co- processor and will be accessed using block I/0 operations. eZ80 chips are not currently available but should be by the time you read this article. The eZ80 has an interesting mode called the Address and Data Long (ADL) mode. In this mode, most of t!1e eZ80 registers are 24 bits, as shown 64 SEPTEMBER 2ooo Embedded Systems Programming for the context switch of tl1e eZ80. I excluded saving the MAC registers for sake of comparison. You may notice that a context switch is identical to the Z80. However, in ADL mode, the 24- bit registers will be appropriately pushed and popped. Note t!1at it's assumed that the 24-bit PC register is already on the top of the stack of tl1e task to suspend. I was able to get an advanced copy of the list of instruc- tion execution times for the eZ80, enabling me to determine how long a context switch takes to execute. To save and restore all the registers, I came up witll a context switch time of 163 clock cycles (about 6.5JlS at 25MHz). Head to head The eZ80 has a more convenient addressing scheme t!1an eitller tlle 180-class processors or the Rabbit 2000 and offers a larger linear add• ·ess space (16MB vs. 1MB). From a perfor- mance standpoin t, one could make a case that the 180-class processors and the Rabbit would be faster (at t!1e same clock speed) than the eZ80 because you generally only need to load tlle memory bank once and use a 16-bit addre s to access a number of

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