EETimes

Embedded Systems September 2000 Vol13_10

Issue link: http://dc.ee.ubm-us.com/i/71837

Contents of this Issue

Navigation

Page 57 of 229

FIGURE 6 Context switch on a Z80 processor PC AF _ _J I DE--~· 1 l BC , ·i - HL BC' ··!i ~~: ·-:!: IX AF' -j, IY 1 ~· . -- --- j -- 1 -I ,I I _ B '- D H / F' Low Priority Task TCB The kernel disables interrupts to protect critical sections of code. Thus, the proces or must thus have instruc- tions to disable and enable interrupts. The Z80 provides two instructions: DI and EI, respectively. What if the pro- grammer had interrupts disabled before calling a function provided by the kernel? Unfo rtunately, the Z80 doesn't provide an easy way to pre- se rve the state of the interrupt disable flag and restore it upon completion of the cri tical secLion. Because of this, in terrupts on the Z80 a re always enabled after leaving a cri tical section . Fortunately, most of the time, this is the way you would wan t it. The Rabbit 2000 (described later) is th e only Z80 derivative that can preserve the state of the interrupt disable flag. The Z80 provides a number of reg- isters that can be used to indi1·ectly address memory, making it a natural fo r poin ter manipulation. A kernel needs RAM to store data stmctures and to maintain a stack for each stack. On a Z80, a kernel uch as pC/ OS-11 requires as little as 1K of RAM fo r inte rn al structures (task PC AF BC DE HL AF' BC' DE' addres space is spli t in to tl1ree areas: Common Area 0, Bank Area, and Common Area 1. The size of each of these can be adjusted with a granular- ity of 4KB. The MMU is con£igured through three 8-bi t I/ 0 ports, which Hi tachi calls registe rs-CHAR, BBR, and CBR. Common Area 0 is designed fo r ! ISRs and other code that cannot be banked, such as kernel services. This region always starts at address OxOOOO in the logical address space and always translates to physical address OxOOOOO. The starting address, and U1US the High Priority Task TCB stacks excluded). Where code space (ROM) is concerned, a minimal con- figuration for pC/ 0 -II would requi re about 3K. Other operating systems may require additional RAM and/ or ROM. Hitachi 64180 As previously mentioned, the Hitachi 64180 processor was introduced in the mid '80s. Hi tachi has stopped promot- ing the 64180 in the U.S. and seems to be concenu·aLing on the H8 and SH processor families. ZiLOG has been pushing many Zl 80 derivative prod- ucts, all based on Hitachi ' original design, having diffe rent complements of on-chip peripherals. Apart from its on-chip peripherals, a 180 class proce or adds value by integi·ating an on-chip MMU. Again, although called an MMU, tl1e 180-class processors only implement memory banking. Figure 6 shows how th e MMU translates a 64KB logical address space into a 1024KB physical memory space. A '180 class processor can only address 64KB of memory at any given time. The 64KB logical 56 SEPTEMBER 2000 Embedded Systems Programming size, of tl1e other areas is established by tl1e common/ bank area register, or CBAR. The upper nibble (four bi ts) of the CBAR sets tl1e starting address in the logical address space of Common Area 1. In otl1er words, i£ tl1e upper nibble of the CBAR is et to Ox8 then Common Area 1 starts at Ox8000. The lower nibble of tl1e CBAR sets the starting address of the Bank Area. For example, if the lower nibble of CBAR is set to Ox4 tl1en the Bank Area starts at Ox4000. To achieve the layout of tl1e logical address space shown in Figure 7, tl1e CBAR would be initialized to Ox84 in the startup code and would not be changed at run time. Common Area 1 is generally used to hold data (RAM) . The common base registe r, or CBR establishes the starting address of Common Area 1 in the physical addres space. The map- ping of logical address to physical address fo r Common Area I is given by: PhysicaLAddress LogicaLAddress; (CBR << 12) + Your application can change the value of the CBR at n111 time and thus poin t to a diffe rent physical block of memory in the physical address space. However, the CBR is generally set once at startup. Finally, we get to the bank base reg- ister, or BBR. Like the CBR, this regis- ter allows your application to view a "window" of physical memory (could

Articles in this issue

Archives of this issue

view archives of EETimes - Embedded Systems September 2000 Vol13_10