EDN, May 26, 2011

Issue link: http://dc.ee.ubm-us.com/i/43174

Contents of this Issue


Page 44 of 63

POWER MANAGEMENT | ANALOG & RF | INTERFACE & CONNECTIVITY | CLOCKS & TIMING | MEMORY & LOGIC | TOUCH & USER INTERFACE | VIDEO & DISPLAY | AUDIO Integrated Device Technology FemtoClock NG – When a Trillionth Of a Second is Just Too Long 0.168 ps RMS Phase Noise (12k - 20M) The FemtoClock Next Generation (NG) clock synthesiser family allows engineers to generate almost any output frequency from a fixed frequency crystal, and to meet the challenges of the most demanding tim- ing applications. Use of a single source to generate mul- tiple clocks often leads to increased susceptibility to power supply noise and restrictions on multiplication factors. IDT's technology effectively eliminates these problems by doubling the power-supply noise rejection (PSNR) of previous genera- tion devices while also introducing the po- tential for virtually limitless customization of output frequency. An innovative fractional multiplier architecture introduces the flexibility for PLL engineers to generate any output fre- quency from any input frequency. And the advanced design of the FemtoClock NG family achieves greater than 80 dB of PSNR to make the devices immune to power-supply noise. Other performance benefits of FemtoClock NG technology include low power consump- tion and a clocking performance of under 0.5 ps RMS phase noise jitter! The devices offer standard outputs such as differential LVPECL, LVDS and single-ended LVCMOS, providing a precise fit to any application. With FemtoClock NG technology, IDT has eliminated the most challenging aspects of silicon-based clock design and introduced an unprecedented level of flexibility for clocking in high-performance applications. Integrated Device Technology The Analog and Digital Company™ For more information visit us online at www.IDT.com

Articles in this issue

Links on this page

Archives of this issue

view archives of EDN - EDN, May 26, 2011