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EDN, May 26, 2011

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typical 48-line VDSL2 terminal in a 10-Gbps backhaul connection. The differential I/Os on the FPGA support a data-transmission speed of 884 Mbps. Along with built-in LVDS transceivers and XAUI-sublayer logic, the FPGA internally implements two buffering and packet-conversion func- tion blocks and two Ethernet MAC (media-access-control) blocks. All four of these blocks consume less than 15,000 look-up tables. This relatively high ratio of SERDES-to-look-up-table resource requirements is characteris- tic of many implementations of high- speed SLVS bridging in DSLAM (digi- tal-subscriber-line-access-multiplexer) applications. Along with adequate I/O flexibility to implement robust SLVS ports, it is useful for the FPGA fam- ily to have members that emphasize high-speed-I/O-pin count rather than logic-cell count. A number of features, including low differential-mode signal swing and low common-mode voltage, provide lower power dissipation for SLVS ports than that of LVDS ports. This advantage is leading to wide use of SLVS within the communications/networking commu- nity, especially on the latest generation of SOCs (systems on chips). FPGAs provide a flexible and economical implementation for a data-transmission interface and for protocol bridging, so it is important for designers to understand how to implement an SLVS interface in an FPGA. Design engineers should carefully consider an FPGA's I/O fea- tures and select the right device from commonly available LVDS-compatible systems to implement the lower-power SLVS interface. Features such as wide input common-mode range, built-in differential-termination load, program- mable SLVS drive-current output, and high SERDES-to-logic ratios can have a substantial effect on board-level imple- mentation of SLVS links.EDN REFERENCES 1 LVDS Owner's Manual, Fourth Edi- tion, National Semiconductor, Spring 2008, http://bit.ly/gu6blc. 2 Goldie, John, "The Many Flavors of LVDS," National Semiconductor, 2011, http://bit.ly/hHEr9k. 3 "Scalable Low-Voltage Signaling (SLVS) standard for 400 mV, JESD8- 13," JEDEC Solid State Technology Association, October 2001, http://bit. ly/egKcZF. 4 "Scalable Low-Voltage Signaling with Lattice SC/M," Application Note 8085, Lattice Semiconductor, April 2011. AUTHOR'S BIOGRAPHY Feng Chen is an FPGA strategic-marketing manag- er at Lattice Semiconductor Corp (Bethlehem, PA), with responsibility for the vertical wireless-base-sta- tion and interface-intellectual-property markets. Chen has more than 15 years of experience in the semiconductor industry and held several positions at CebaTech, LSI Logic, and Alcatel before joining Lat- tice in 2010. He has a master's degree in electrical engineering from Texas Tech University (Lubbock, TX) and a master's degree in business administration from the University of Texas—Dallas. This Tiger is as solid as a rock! Low power Intel Atom Z5xx processor on a PC/104- VersaLogic's new "Tiger" single board computer is compact and rugged on a 3.6" x 4.5" PC/104- form factor. Featuring the low power Intel® Atom™ Z5xx (Menlow XL) processor, the Tiger packs powerful 1.6 GHz performance backed by legendary VersaLogic quality. It's available in both commercial (0º to +60ºC) and industrial (-40º to +85ºC) temperature versions! Intel Atom Z5xx processor up to 1.6 GHz Low power, 6W (typical) True industrial temp. version (-40º to +85ºC) High-performance video and HD audio Gigabit Ethernet Up to 2 GB DDR2 RAM PCI & ISA expansion Fanless operation Add VersaLogic's long-term (5+ year) product availability guarantee and customization options and feel the power of the Tiger! With more than 30 years experience delivering extraordinary support and on-time delivery, VersaLogic has perfected the art of service, one customer at a time. Experience it for yourself. Call 800-824-3163 for more information! 800-824-3163 | 541-485-8575 | www.VersaLogic.com / tiger Recipient of the VDC Platinum Vendor Award for fi ve years running! form factor MAY 26, 2011 | EDN 37 Pl u s P lus

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