EDN, May 26, 2011

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A30_EDN_2-25x10:A30.qxd 4/1/11 1:05 PM Page 2.5V TYPICAL 220 R1 + 6-mA LVDS − 220 R1 ON-CHIP LVDS − + Z0 50 2.5V TYPICAL R3 15 ON-CHIP − + Z0 50 R2 47 100 − SLVS PEER R2 47 R3 15 SLVS DIFFERENTIAL + Figure 3 An FPGA with internal termination offers a simple connection to an SLVS peer device. Now... up to 150 Watts • 0.4 Watts to 150 Watts Power Transformers • 115V/26V-400/800 Hz Primary • Secondary Voltages 2.5V to 300V • Manufactured to MIL-PRF 27 Grade 5, Class S, (Class V, 1550 C available) • Surface Mount or Plug-In • Smallest possible size driver buffer typically must inject more than the LVDS-nominal 3.5 mA of cur- rent into the off-chip differential traces. A current-driver buffer meeting this requirement is not commonly available with a traditional LVDS-compatible FPGA-I/O port. One SLVS-interface implementa- tion uses an FPGA in which the fea- tures of the LVDS inputs conform to the signaling requirements to directly connect to SLVS transmitters (Figure 3). The internal differential termina- tions are available for inputs on all sides of the device. Common-mode- and differential-voltage ranges sufficiently cover the SLVS output spec, enabling the inputs to receive data streams as fast as 2 Gbps without any additional board components. The FPGA also provides programmability of differential-current output at 2, 3.5, 4, and 6 mA. This example uses a 6-mA driver current with the off-chip termination circuitry to emulate the SLVS requirements. Table 1 details SLVS-specification con- formance for this example. SLVS APPLICATIONS EDN 110526DF1 Figure 3 DIANE The SLVS interface finds application in, for example, data communications and video/image displays requiring high- speed and low-power data channels. An FPGA device with SLVS-compatible transceivers plays an important role in bridging the SLVS I/O on a standard IC product to other data protocols. The recent design-in of a Lattice (www. latticesemi.com) SC/M FPGA with a Broadcom (www.broadcom.com) VDSL2 (very-high-bit-rate-digital- subscriber-line) reference line card demonstrates how the FPGA provides SLVS interfacing and XAUI (10-Gbps- attachment-unit-interface) PHY (physical)-layer bridging functions. On the VDSL2 reference design, the FPGA implements six SLVS links (Figure 4). The FPGA device func- tions as a bridge between the SLVS TABLE 1 SLVS INPUT- AND OUTPUT-SPECIFICATION CONFORMANCE Characteristic Device LVDS input (mV) PICO Electronics, Inc 143 Sparks Ave., Pelham, NY 10803 Call Toll Free 800-431-1064 E Mail: info@picoelectronics.com FAX:914-738-8225 Minimum common-mode voltage Maximum common-mode voltage Minimum differential voltage Maximum differential voltage Characteristic Minimum common-mode voltage Maximum common-mode voltage Minimum differential voltage Maximum differential voltage Delivery - Stock to one week INDUSTRIAL • COTS • MILITARY 50 2350 100 2400 Output with resistor network (mV) 150 280 180 280 SLVS output (mV) 150 250 140 270 SLVS input (mV) 70 330 140 450 Surface Mount and Plug-In 400 / 800 Hz Transformers www.picoelectronics.com See Pico's full Catalog immediately

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