EDN

EDN, May 26, 2011

Issue link: http://dc.ee.ubm-us.com/i/43174

Contents of this Issue

Navigation

Page 31 of 63

a current source in the transmitter toggles polarity as the signal changes state, driving the wire loop (Figure 1). Most of the drive current flows through the receiver-side termination resistor, assuming high impedance at the op amp's input for dc current. The voltage drop across the termination resistor is proportional to the drive current; when the transmitter toggles, the receiver's op amp detects the change in polarity, recognizing the change in signal state at the transmitter's input. LVDS offers high noise tolerance because it uses a pair of differential trac- es to provide common-mode rejection. Both the speed of data transmission and the power dissipation closely relate to the voltage swing across the termina- tion resistor, which is 350 mV, or 700 mV p-p nominal, over a 100Ω resistor for a typical LVDS loop. LVDS channels have a low suscep- tibility to external noise because dis- tant noise sources tend to add the same amount of voltage to both lines, so the difference between the voltages remains the same. The low common-mode volt- age is the average of the voltages on the two traces—approximately 1.25V. The transmitter sets the common-mode voltage as an offset voltage from ground. The 350-mV differential voltage causes the LVDS to consume static power in the LVDS load resistor, depending on the 1.25V offset voltage and 350-mV differential-voltage swing. The JEDEC JESD8-13 SLVS-400 standard defines a point-to-point signal- ing method. SLVS uses smaller voltage swings and a lower common-mode volt- TRANSMITTER 3.5 mA AT A GLANCE ↘ SLVS (scalable low-voltage sig- naling) offers significant power sav- ings over LVDS (low-voltage differ- ential signaling). ↘ SLVS reduces both signal-swing and common-mode voltages. ↘ Some FPGAs can implement SLVS I/Os. age than LVDS. The 200-mV, or 400-mV- p-p, SLVS swing contributes to a reduc- tion in power and is common in RSDS (reduced-swing-differential-signaling) standards. The RSDS standard reduces the swing from 350 mV to 200 mV with the same 1.25V common-mode offset of the LVDS standard. SLVS goes further and also reduces the common-mode volt- age. The SLVS nominal common-mode voltage of 200 mV provides a consider- able decrease in quiescent power. The combination of a smaller signal swing and low common-mode voltage produces much lower power consumption. To illustrate this point, consider that a 6-Gbps LVDS SERDES (serializer/ deserializer) link consumes approximate- ly 250 mW. A typical SLVS pair running at 800 Mbps consumes approximately 15 mW. Even eight 800-Mbps SLVS links running in parallel for a combined speed of 6.4 Gbps consume only about 120 mW—less than half the power consump- tion of the LVDS implementation. FPGA DESIGN FOR SLVS To build an SLVS-compatible interface, a designer must consider whether the + 100 − Figure 2 FPGAs can use differen- tial termination (a) but should use both differential and common- mode termination (b) for SLVS. Z0 2Z0 Z0 (a) OFF-CHIP 32 EDN | MAY 26, 2011 ON-CHIP EDN 110526DF1 Figure A DIANE − + Z0 (b) OFF-CHIP ON-CHIP Z0 Z0 VCM Z0 − + RECEIVER target FPGA device provides sufficient hardware resources and flexibility at its I/O ports for both receiver and trans- mitter implementation. Embedded dif- ferential termination is preferable in an SLVS receiver to minimize the number of onboard components that directly connect to its transmitter peer. More important, many FPGA receivers target use in LVDS, so designers should ensure that the FPGA receiver's differential and common-mode range covers the entire SLVS output specification. The FPGA's differential output port also must be able to source the drive cur- rent for the proper SLVS level with an external coupling-resistor network. Like LVDS, SLVS requires a load termination at the receiver but does not specify whether the termination is inside or outside the receiver. Most FPGA devices typically use both built- in and board resources to build an SLVS interface to industry-standard devices. To achieve cleaner board interconnec- tions and robust system performance, an FPGA device that contains built-in differential termination in the receiv- er implementation has an advantage (Figure 2). The programmability of the output current source is critical for an SLVS transmitter. You must program the differential driver current to a value that emulates SLVS requirements. The design typically uses an onboard resis- tor network to adjust the swing and common-mode voltages that the SLVS receiver requires. To compensate for the power consumption of the onboard resistor network, the current-source Figure 1 The LVDS transmitter drives the line from an internal current loop.

Articles in this issue

Archives of this issue

view archives of EDN - EDN, May 26, 2011