EDN, May 26, 2011

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IMPLEMENTING AN T SLVSRANSCEIVER SLVS PROVIDES AN IMPORTANT NEW ALTERNATIVE TO LVDS FOR HIGH-SPEED SIGNALING, BUT IT PLACES HEAVY DEMANDS ON I/O CIRCUITRY, ESPECIALLY IN FPGAs. YOU MUST WATCH THE DETAILS. BY FENG CHEN • LATTICE SEMICONDUCTOR CORP O 30 EDN | MAY 26, 2011 ver the past two decades, the explosive growth in demand for data bandwidth has led to a variety of data-transmission stan- dards. Lower implementation costs and the ability to transfer more data bits with less power consumption are the primary goals of any data-transmission standard. Since National Semiconductor's (www.national. com) introduction of LVDS (low-voltage differential signaling) in 1994, it has become the most widely adopted data-transceiver standard in the industry for delivering gigabit performance levels at milliwatt power levels. Although the company crafted the technology for easy implementation in the equipment of a previous decade, it has its limitations. Addressing the limitations of LVDS as a generic stan- dard, several variations have evolved to meet application-specific require- ments. In October 2001, the JEDEC (Joint Electron Device Engineering Council) Solid State Technology Association published the SLVS (scal- able-low-voltage-signaling) standard for 400-mV operation. SLVS inherits from LVDS low noise susceptibility. It also boasts a scaled-down 400-mV sig- nal swing—versus the 700-mV swing of LVDS—and includes a ground refer- ence. This combination results in lower power consumption for transmission. The interface normally requires a 0.8V power rail, which is commonly available in submicron silicon devices. Designers can achieve a data rate as high as 3 Gbps or beyond over a range that is com- patible with the size of a typical PCB (printed-circuit board). This combina- tion of features makes SLVS appropri- ate for use in high-speed, low-power transmission for interdevice data links on a PCB. This utility also makes SLVS impor- tant in the FPGA world. Designers often use FPGA devices, due to their feature-rich I/O ports, for datapath interfacing and protocol bridging. With the increasing popularity of SLVS in data-channel design, designers hope to achieve economic and robust FPGA design for SLVS-transceiver applica- tions. Most FPGAs support the tra- ditional LVDS interface. However, designers cannot program all modern FPGA-I/O structures to drive current at SLVS requirements for output, and not all provide a built-in differential termi- nation to receive SLVS input with few external components. To determine the abilities of an FPGA-I/O design to sup- port SLVS, you must look deeper into both the standard and the I/O structures that today's programmable devices use. LVDS/SLVS OVERVIEW The LVDS data-transmission standard is a mature technology and has become the most common transceiver inter- face in applications such as video, stor- age, and data communications, which require transmission of large amounts of data. In a point-to-point LVDS link, IMAGE: GETTY IMAGES

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