Electronic Engineering, Nov. 1989

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DESIGN Solid State sileo By Stan Baker Vive Componic Paris - It's time again for the world's only significant components conference and exposition, the grand Salon tks ComjJosantes. TIlis year, though, the French have given the venerable show anew, high-tech name: Comp<>nic. Held each odd-numbered year, Componic is dedicated to components-passive, active, discrete and integrated. Over the years, a number of introductions have been announced here by American and Japanese producers, for exlubitors here know the whole world has come to see, touch, learn and buy. End products are being merchandised, but so are ideas and know-how. Trade fairs are fun and useful to attend in Europe. Gatherings such as Componic, the Hanover Fair and Munich's Electronica have retained hundreds of years of merchandising tradition. And in contrast to U.S. trade shows, real business gets done at European fairs. Exhibitor booths pack all the trappings to promote negotiations, including food and drink. Attendees of American shows must travel to hotel suites or restaurants to get such treatment. Each exhibitor in Europe can create his own environment for display, discussions and negotiations. And outside the exhibits, the facilities are complete with good restaurants and small shops for the business travelers' necessities. Since the dark ages, major European fairs have presented the art, goods and ideas from the known world of the time. The high technologies of each age were shown and traded, from textiles and printing to steam engines and automobiles. European trade fairs are where technology meets the market. Motorola chose this every-other-year meeting to announce its 4-Mbit DRAM, its 12-ns CMOS SRAMs and its customer driven ASICs program. It also gave more details of the Typhoon 1,024-pin tester partnership with Schlumberger. The recent emphasis on getting into DRAMs points out that all but two broadline semiconductor companies (National Semiconductor Corp. and Harris Corp.) have decided they need DRAMs to remain viable. SGS-Thomson is not in DRAMs yet but is fabricating samples of its I-Mbit design and finalizing its decision this month on re-entering the DRAM market. It plans to announce its program in the first quarter of next year and, if it can't find a partner, may do it alone. Jim Norling, executive vice president of Motorola's Semiconductor Sector, explained that when Motorola dropped out of DRAMs in the mid-1980s it "literally decided on the same day to get back in." Meaning that Motorola recognized it had to trash what it had and find out how to do it right. The path it chose is through a venture in Japan with Toshiba. With the 4-Mbit and other generations, apparently, Toshiba will develop and start production, while Motorola will resell under its own name and then get die to test and assemble. A Motorola executive also indicated that the company will build an advanced test and assembly plant in Japan soon. And after that, it "will likely build a DRAM fab in Japan." Such an investment would put Motorola's DRAM foot in Japan much as TI's has been for many years. It appears that the way for Motorola to wean itself from Toshiba involves developing its own Japanese DRAM operation. The company will continue to depend on Toshiba for plain vanilla SRAMs, but it will depend on its own program for the high-speed versions. Motorola executives said digital signal processors this year will become standard features in many personal computers and workstations. Jack Browne, Motorola's hypertense director of microprocessor marketing, projected the 88OOO-based systems in 1991 will achieve 60 to 80 Mips, with ECL pushing that to 100 Mips in 1992. He warned we will have to get used to the term "Bips," for the ECL version will push parallel-processing systems to over 1,000 Mips. And by 1993, 88000 versions made with BiCMOS are to exceed the speed of ECL versions by 20 percent to 40 percent. But until then, we are still waiting for the first generation of 88000 systems. "We are getting them together," said Browne. TriQuint UpS cell library By AARON FISCHER Beaverton, Ore. - TriQuint Semiconductor Inc. is beefing up its QLSI GHz LSI standard-cell library. The company now handles applications to 10,000 equivalent gates and has added standard-cell ROM and linear function cells. "With toggle rates greater than 2 GHz, clock speeds two to three times faster than advanced silicon bipolar gate arrays and power- T he move to 10,000 gates addresses computers and instrumentation. per-gate levels that are 50 percent lower, this is clearly the fastest LSI offering in production today," said marketing manager Louis Pengue. The move to 10,000 gates has been made "to address the computer and instrumentation markets," Pengue said. Up to 4 kbits of standard-cell ROM can now be added to a chip to boost flexibility. According to the company, "ROM is ideal for implementing such single-chip functions as an accumulator/ ROM, a key building block for direct digital synthesis." The linear functional cells represent a costeffective approach to mixed-signal ICs. A range of amplifiers, laser drivers, transimpedance amps, comparators, data converters and oscillators are available. Each functional block has been characterized and can be implemented as it stands or be modified to meet -a particular need. When modification is in order, TriQuint will supply all design layout changes. QLSI cells now pack on-board ROM. The QLSI standardcell library contains an assortment of gate and logic mac- a standard-cell IC starts at 55,000 and includes design ros in three speed/ power families, as weU as a family manuals and workstation softof 110 cells that can interlace with ware. Turnaround time typicalECL, TTL and CMOS. The li- ly runs 12 to 14 weeks for five brary runs on Mentor and Daisy tested and packaged parts and a workstations. Standard-ceU ICs high-speed evaluation board. are available as die or packaged. Nonrecurring engineering for Louis Pengue (503) 644-3535 First chip from Dutch compiler By ROGER WOOLNOUGH Son, Netherlands - Sagantec Europe B.V., a small Dutch startup that launched a silicon compiler a year ago, has given details of the first IC designed for a third party using the system. The chip is for a major European data-network operator and forms part of a dataencryption unit that prevents unauthorized or maliciou access to data lines. Sagantec was founded in 1981 by Antek Szepieniec, a CAD researcher at the Technical University of Eindhoven. Szepieniec led a team that developed the company's first product, a software tool called Saga. Work on silicon compilation began in 1984, and the first release of the ASA silicon compiler package was developed in 1987. ASA was launched commercially in November 1988. The silicon compiler is a knowledge-based tool for the design of complex ASICs, typically upward of 30,000 transistors. It uses a top-down approach to IC design, working from high-level functional and logical descriptions. The compiler itself contains the necessary chip-layout knowledge, allowing the engineer to fashion the design in a free-thinking way. Alternative approaches to system implementation can be rapidly assessed and simulated before detailed design is undertaken. Sagantec claims that ASA is the only compiler that is not based on a specific production technology from a particular foundry. The data-encryption IC was processed in 1.5-micron doublemetal CMOS at a European foundry and packaged in an 84-pin LCC. The chip occupies 84 quare mm of silicon and contains over 56,400 transistors (equivalent to about 14,000 gates). A SA is not based on any specific production technology from a particular foundry. Two conflicting requirements faced the data-encryption de ign team. Long encryption keys are desirable from a security point of view, but they require long and complex algorithms to encrypt and decrypt data. The conventional approach is to use a dedicated microprocessor with algorithms implemented in ROMbased software. But even highspeed microprocessors cannot match the on-line speed requirements of present-day wide-bandwidth communication lines. The answer was to u e an application-specific cipher chip and to encrypt and decrypt data with dedicated hardware. Designing an ASIC with inherently long algorithms implemented directly onto the silicon requires a highly structured de ign methodology. The ASA compiler was able to provide that. The Sagantec input description language (SID) has a Pascal-like syntax and allows the design specification to be entered progressively and at a high level of abstraction. Simulation at each level is possible to verify the design and evaluate alternative implementations. In aU, some 2,500 lines of input code were required to define the encryption chip for the ASA compiler. Production versions of the chip could be smaller than the fir t design. A recompilation for a CMOS process with a 1.2-micron channel width reduced the die size by almost 50 percent, to 43 square mm. That took less than two man-weeks to complete. Sagantec is based in Son-a few miles north of Eindhovenwhere it employs more than 40 people. Field-sales and technicalsupport personnel have been appointed for the Benelux countries, West Germany and Britain, with other European regions to foUow soon. The company is also active in research into hardware-description languages, working with other European companies and universities in the Economic Community's Esprit project. November 20, 1989 Ekctronic Engineering Times 41

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