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Design News, March 2013

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An increase in resistance indicates a breakdown in electrical integrity via cracks in the copper circuit. A standard coupon design for this test utilizes a chain of 32 plated throughholes, which has long been considered to be the weakest point in a circuit when subjected to thermal stress. Thermal cycle studies done on standard FR4 boards with 0.8-mil to 1.2-mil copper plating have shown that 32 percent of circuits fail after eight cycles (a 20 percent increase in resistance is considered a failure). Thermal cycle studies done on exotic materials show significant improvements to this failure rate (3 percent after eight cycles for Cyanate Ester), but are prohibitively expensive (five to 10 times material cost) and difficult to process. An average surface-mount technology assembly sees a minimum of four thermal cycles before shipment, and could see an additional two thermal cycles for each component repair. It's not unreasonable for a SMOBC board that has gone through a repair and replacement cycle to reach a total of nine or 10 thermal cycles. The TCT results clearly show that the failure rate, no matter what the board material, can become unacceptable. Printed circuit board manufacturers know that copper electroplating isn't an exact science — changes in cur- rent densities across a board and through numerous hole/via sizes result in copper thickness variations of up to 25 percent or more. Most areas of "thin copper" are on plated-hole walls — the TCT results clearly show this to be the case. Using heavy copper circuits would reduce or eliminate these failures altogether. Plating of 2 oz/ft2 of copper to a hole wall reduces the failure rate to almost zero (TCT results show a 0.57 percent failure rate after eight cycles for standard FR4 with a minimum of 2.5-mil copper plating). In effect, the copper circuit becomes impervious to the mechanical stresses placed on it by the thermal cycling. Thermal Management As designers strive to obtain maximum value and performance from their projects, printed circuits are becoming more complex and are driven to higher power densities. Miniaturization, use of power components, extreme environmental conditions, and high-current requirements increase the importance of thermal management. The higher losses in the form of heat, that's often generated in the operation of electronics, has to be dissipated from its source and radiated to the environment; otherwise, the components could over- REGISTER: www.star-global-conference.com REASONS TO ATTEND THE BIGGEST CAE EVENT OF THE YEAR: • Power Up Your Engineering Skills Build your own training day agenda, choose from 15 Best Practices Workshops, each of which is a deep-dive into a specific area of engineering simulation Follow us online. For more information: info@cd-adapco.com ents elopm logy t dev no Lates CFD Tech he & re t Explon the CAE i O ARCH 20 M 18 13 AND • Learn as over 50 leading industrial experts reveal the secret of their engineering success, exploring their simulation process and demonstrating in detail the tangible benefits of STAR-CCM+ 2013 ton Shera Lake 20 Bu ista ena V ORL • Network with experts, the STAR Global Conference is one of the world's largest gatherings of simulation experts, it is also your opportunity to meet with CD-adapco Management, Software developers and Support engineers Resor t

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